This invention relates generally to radiation imager arrays and in particular relates to a common electrode structure in an x-y addressed imager array that is configured to have reduced common electrode impedance and low magnetic loop area for returning signal currents and further configured for ready determination of the location of short circuits between address lines and the common electrode.
Complex electronic devices are commonly formed on substrates in fabrication processes involving the deposition and patterning of multiple layers of conductive, semiconductive, and dielectric materials so as to form multiple individual electronic components. For example, large area imager arrays (e.g., having an area of about 25 cm.sup.2 or more) are commonly fabricated on a wafer and contain photodiodes and circuitry for reading the output of the photodiodes, such as address lines and switching components (e.g., thin film transistors (TFTs)). In such an array a common electrode layer extends over the top of almost the entire pixel array, with the off-the-wafer contacts for the common electrode being disposed at the four corners of the common electrode.
Such an arrangement for the common electrode, with off-the wafer contacts disposed at the four corners, necessitates that all readout and drive circuitry for the various address lines (an imager with an area of about 25 cm.sup.2 may have one thousand or more address lines) be coupled to one of the four contact points, an arrangement that can result in a high impedance common electrode and large magnetic loop area for low-level returning signal currents. This arrangement can result in significantly higher susceptibility of the detector and readout electronics to radiated electric and magnetic fields generated by external circuits (that is, EMI). High common electrode impedance can further lead to increased susceptibility of the detector and readout electronics to conducted interference, particularly when defects within the detector array are scanned (or read out).
Further, during fabrication defects in such imager arrays can result from, among other causes, impurities in materials deposited to form the various components. One example of such an impurity-based defect is a short circuit between the common electrode and an underlying address line in the pixel array. Such short circuits disrupt the desired electrical connections between devices in the array and seriously degrade the performance of one or more of the individual electronic components on the wafer, often to the point of making an entire wafer unusable.
It is often difficult to locate a short circuit to the common electrode as the electrode extends over substantially the entire upper surface of the array, thus covering the entire length of each address line, including the address line to which it is shorted. Traditionally, a detailed visual inspection of the array has been required to attempt to locate the short circuit, a process that is time consuming and not always successful in locating the site of the short circuit. Procedures and imager structures that enable one to lessen the time to find the defect hasten the repair effort and thus reduce the overall cost of fabricating the array and improve the manufacturing yield of the array fabrication process.
One object of this invention is to provide an imager assembly that has a structure with multiple electrical contacts to the common electrode disposed along the sides of the imager at points in addition to the corners of the imagers to facilitate the localization of a short circuit between the common electrode and an address line.
A further object of this invention is to provide an imager assembly that has a structure with multiple electrical contacts to the common electrode disposed along the sides of the imager at points in addition to the corners of the imagers to provide low-impedance and small magnetic loop area return path common electrode contact points for readout circuitry for the data lines of the array.